1. Field of the Invention
The present invention relates to a thin film transistor having an active region interposed between insulating films, and a method for fabricating the same. More particularly, the present invention relates to a MOS thin film transistor used for an active matrix substrate, a thin film integrated circuit in general, an image sensor, and the like.
2. Description of the Related Art
In recent years, efforts have been made to form high-performance semiconductor elements on an insulating substrate such as a glass substrate or on an insulating film for realization of a large-scale liquid crystal display device with high resolution, a monolithic liquid crystal display device with a driver circuit formed on the same substrate for cost reduction, a fit-type image sensor with high speed and high resolution, a three-dimensional integrated circuit (IC), and the like. As a semiconductor element used for these devices, a MOS thin film transistor (TFT) using a silicon semiconductor thin film as an active region is generally used.
A typical configuration of such a MOS TFT is of a coplanar type as shown in FIG. 6. The coplanar type transistor includes the following components. A silicon thin film which is to be an active layer 9 is formed on an insulating substrate 1. The active layer 9 is divided into two types of regions, i.e., a source region 14 and a drain region 15 which are doped with n-type or p-type impurities, and a channel region 13 which actually serves as an active region of the transistor. A gate insulating film 10 is formed to cover the active layer 9, and a gate electrode 11 is formed above the channel region 13. An interlayer insulating film 17 is formed to cover the resultant substrate, and a source electrode 18 and a drain electrode 19 are formed on the interlayer insulating film 17.
In an IC fabrication process, in general, an Si single-crystalline substrate is used and the surface of the substrate is oxidized at high temperature to obtain a gate insulating film. The resultant gate insulating film made of silicon oxide has significantly high quality, and the interface between the active layer (Si substrate) and the gate insulating film is kept clean, providing an excellent interface characteristic.
On the contrary, in the TFT fabrication process described above, the gate insulating film 10 needs to be formed by deposition. This makes it basically difficult to obtain such a high-quality silicon oxide film as that obtained by the thermal oxidation in the IC fabrication process. In the TFT fabrication process, also, the active layer needs to be patterned before the formation of the gate insulating film as is observed from FIG. 6. It is not possible, therefore, to form the gate insulating film in succession with the formation of the active layer 9. The resulting interface between the active layer 9 and the gate insulating film 10 does not provide as good characteristics as those obtained in the IC fabrication process. As a result, the threshold voltage of the TFT is unstable.
A method for fabricating a CMOS-FET (complementary metal oxide semiconductor field effect transistor) in an SOI (silicon-on-insulator) process using an Si single-crystalline substrate has been proposed in Japanese Laid-Open Publication No. 5-121681. The technique disclosed in this publication is restricted to the CMOS-FET fabricated in the SOI process. According to this technique, in order to reduce a short channel effect, fixed charges in an underlying oxide film formed on the Si substrate are utilized. That is, negatively charged ions are implanted in the underlying oxide film for an n-channel FET, while positively charged ions are implanted for a p-channel FET.
In the MOS TFT, fixed charges in the gate insulating film are one of the factors influencing the threshold voltage of the TFT. However, a silicon oxide film formed by deposition is unstable in quality and includes a number of fixed charges in the film. In general, a film formed by CVD (chemical vapor deposition) includes a number of SiOH groups, where Si dangling bonds act as positive charges. As a result, a semiconductor layer in contact with the gate insulating film becomes an n-type layer under the influence of the positive charges. The threshold voltage of the TFT thus shifts toward a negative value, exhibiting a depletion type characteristic. The "depletion type" is a type where a drain current is allowed to flow when the gate voltage is 0.
The TFT should desirably have at least an enhancement type characteristic, not the depletion type characteristic, when the TFT is used for a thin film IC such as a CMOS inverter circuit, and an active matrix substrate and a driver circuit therefor for a liquid crystal display device. The "enhancement type" is a type where a drain current is not allowed to flow when the gate voltage is 0. In addition to having the enhancement type characteristic, the absolute value of the threshold voltage of the TFT should be desirably as small as possible, to reduce the driving voltage.
In consideration of the above, the threshold voltage of a TFT is typically controlled by directly implanting n-type impurities or p-type impurities in the channel region of the transistor. However, the impurities implanted in the channel region dull the rising of a drain current in the subthreshold region during the operation of the MOS transistor, as well as increasing the leak current during the non-operation thereof. In other words, the driving capability of the transistor itself is lowered in compensation for the control of the threshold voltage.
The method disclosed in the above-mentioned publication where negatively charged ions are implanted for an n-channel FET and positive charges are implanted for a p-channel FET may be applied to the TFT, though the objective of the technique is somehow different from the objective of controlling the threshold voltage of the transistor. In this method, however, since an n-channel TFT and a p-channel TFT are separately controlled, it is difficult to stabilize the difference in the absolute value of the threshold voltage between the n-type and p-type TFTs. Moreover, this method requires two ion implantation steps. This complicates the fabrication process and increases the cost.
In view of the above, an objective of the present invention is to provide a thin film transistor with high characteristic stability, high performance, and low power consumption formed on an insulating surface of a substrate, and a method for fabricating such a thin film transistor.
Another objective of the present invention is to provide a method for fabricating a thin film transistor which can control and optimize the variation in the threshold voltage observed in the thin film transistor in a low-cost simple process in order to realize a larger-size active matrix liquid crystal display device with higher resolution, a driver-monolithic active matrix liquid crystal display device with a driver formed on a same substrate, a thin film IC, and the like.